1. Field
The present disclosure relates generally to clock synchronization, and more specifically to low-power synchronization of divider unit phases.
2. Background
Digital circuits use clocking signals for a variety of reasons. For example, synchronous systems use global clock signals to synchronize various circuits across a board or IC device.
Most systems use one clock generating circuit to generate a first clock signal and a specialized circuit to derive other clock signals from the first clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from an input clock signal.
For example, a transmitter up-converter Local Oscillator (LO) divider, which is based on a thermometer type unit-based design may be utilized. This unit-based divider provides excellent LO leakage and gain control step, as well as excellent LO power consumption for low output power. Such a divider with excellent LO power consumption is increasingly desirable, especially in polar transmitters that are becoming more common for various modulation systems. However, the phases of the divider units therein are not synchronized, and the up-converter output power is not constant at every power up.
In an up-converter divider, with two divider units for example, in-phase power (i.e., amplitude from the up-converter output) may be 6 dB higher. Three divider units may provide a 9.5 dB higher amplitude. However, as phases of the divider units become unsynchronized, these heightened power amplitudes decrease. In fact, if two divider units are 180 degrees out of phase, their output powers will be cancelled out completely.
According to conventional Code Division Multiple Access (CDMA) systems, transmission power of a handset close-loop is controlled with a base station. If the requisite transmission power of handset is unpredictable, the power decisions from the base station will be inaccurate or nonfunctional.